-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.

-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.

--altera translate_off
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;

entity video_gen is
	port (
		clock : in std_logic := '0';
		dout_data : out std_logic_vector(8-1 downto 0);
		dout_endofpacket : out std_logic;
		dout_ready : in std_logic := '0';
		dout_startofpacket : out std_logic;
		dout_valid : out std_logic;
		reset : in std_logic := '0'
	);
end entity video_gen;

architecture rtl of video_gen is

component video_gen_GN is
	port (
		clock : in std_logic := '0';
		dout_data : out std_logic_vector(8-1 downto 0);
		dout_endofpacket : out std_logic;
		dout_ready : in std_logic := '0';
		dout_startofpacket : out std_logic;
		dout_valid : out std_logic;
		reset : in std_logic := '0'
	);
end component video_gen_GN;

begin

video_gen_GN_0: if true generate
	inst_video_gen_GN_0: video_gen_GN
		port map(clock => clock, dout_data => dout_data, dout_endofpacket => dout_endofpacket, dout_ready => dout_ready, dout_startofpacket => dout_startofpacket, dout_valid => dout_valid, reset => reset);
end generate;

end architecture rtl;

--altera translate_on
